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| 82437fx system controller (tsc) and 82438FX data path unit (tdp) timing specification datasheet addendum product features reference information: the information in this document is provided as a supplement to the standard package datasheets published for the intel 430fx pciset. please refer to the standard 430fx datasheet (order number 290518) for tsc and tdp product information and specifications not found in this document. n supports the pentium ? processor at icomp ? index 1110\133 mhz, icomp index 1000\120 mhz, icomp index 815\100 mhz, icomp index 735\90 mhz and the icomp index 610\75 mhz n integrated second level cache controller direct mapped organization write-back cache policy cacheless, 256-kbyte, and 512-kbyte standard burst and pipelined burst srams cache hit read/write cycle timings at 3-1-1-1 with burst or pipelined burst srams back-to-back read cycles at 3-1-1-1-1-1-1-1 with burst or pipelined burst srams integrated tag/valid status bits for cost savings and performance supports 5 v srams for tag address n integrated dram controller 64-bit data path to memory 4 mbytes to 128 mbytes main memory edo/hyper page mode dram (x-2-2-2 reads) or standard page mode drams 4 qword deep buffer for 3-1-1-1 posted write cycles 5 ras lines symmetrical and asymmetrical drams 3 v or 5 v drams n edo dram support highest performance with burst or pipelined burst srams superior cacheless designs n fully synchronous 25/30/33 mhz pci bus interface 100 mbyte/s instant access enables native signal processing on pentium processors synchronized cpu-to-pci interface for high performance graphics pci bus arbiter: piix and four pci bus masters supported cpu-to-pci memory write posting with 4 dword deep buffers converts back-to-back sequential cpu to pci memory writes to pci burst writes pci-to-dram posting of 12 dwords pci-to-dram up to 120 mbytes/s bandwidth utilizing snoop ahead feature n nand tree for board-level ate testing n 208-pin qfp for the 82437fx system controller (tsc); 100 pin qfp for each 82438FX data path (tdp) order number: 297463-001 may 1998
datasheet addendum information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 82437fx system controller (tsc) and 82438FX data path unit (tdp) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1998 *third-party brands and names are the property of their respective owners. datasheet addendum 3 timing specification intel ? 82437fx (tsc) and 82438FX (tdp) contents 1.0 electrical characteristics ........................................................................................ 5 1.1 absolute maximum ratings................................................................................... 5 1.2 thermal characteristics ........................................................................................ 5 1.3 dc characteristics ................................................................................................ 6 1.4 82437fx ac characteristics ................................................................................. 8 1.5 82438FX ac characteristics ...............................................................................13 1.6 82437fx/82438FX timing diagrams ..................................................................15 2.0 timing relationship diagrams ...........................................................................17 2.1 cache timing relationships................................................................................17 2.2 dram timing relationships ...............................................................................23 2.3 additional timing relationships ..........................................................................33 figures 1 clock timing........................................................................................................15 2 propagation delay...............................................................................................15 3 valid delay from rising clock edge ..................................................................15 4 setup and hold times.........................................................................................15 5 float delay ..........................................................................................................15 6 flow through delay ............................................................................................16 7 pulse width .........................................................................................................16 8 output enable delay ...........................................................................................16 9 burst read (l1 line fill), standard sram..........................................................17 10 burst write (l1 cache write-back), standard sram .........................................18 11 back to back burst reads (l1 cache line fills), standard sram.....................18 12 second level cache read miss, write-back, line fill with pipelined burst sram .................................................................................19 13 read miss, l2 cache write-back, line fill, standard sram .............................19 14 burst read, pipelined burst sram.....................................................................20 15 back-to-back reads (l1 cache line fills), pipelined burst sram ....................20 16 back-to-back writes (l1 cache line fills), pipelined burst sram ....................21 17 l2 cache read miss, write-back, line fill, pipelined burst sram ...................22 18 burst read page hit (edo) ................................................................................23 19 burst read row miss (edo)...............................................................................24 20 burst read page miss (edo) .............................................................................25 21 burst read page hit (standard page mode) ......................................................26 22 burst read row miss (standard page mode) ....................................................27 23 burst read page miss (standard page mode) ...................................................28 24 posted burst write page hit................................................................................29 25 burst write row miss ..........................................................................................30 26 burst write page miss.........................................................................................31 27 burst write...........................................................................................................32 28 cpu to pci write cycle ......................................................................................33 29 cpu to pci memory read cycle ........................................................................33 30 pci bus master to dram write cycle ................................................................34 31 pci bus master read from dram.....................................................................35 32 ras only dram refresh cycle .........................................................................35 intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 4 datasheet addendum tables 1 82437fx (tsc) package thermal resistance ..................................................... 5 2 82438FX (tdp) package thermal resistance ..................................................... 5 3 82437fx dc characteristics................................................................................. 6 4 82438FX dc characteristics................................................................................. 7 5 host clock timing; 60 mhz and 66 mhz (82437fx) ............................................ 8 6 cpu interface timing; 60 mhz and 66 mhz (82437fx) ....................................... 9 7 second level cache timing; 60 mhz and 66 mhz (82437fx) .......................... 10 8 dram interface timing; 60 mhz and 66 mhz (82437fx) .................................. 11 9 pci clock timing; 60 mhz and 66 mhz (82437fx)............................................ 11 10 pci interface timing; 60 mhz and 66 mhz (82437fx)....................................... 12 11 tdp interface timing; 60 mhz and 66 mhz (82437fx) ..................................... 13 12 host clock timing; 60 mhz and 66 mhz (82438FX) .......................................... 13 13 command signal timing; 60 mhz and 66 mhz (82438FX) ................................ 14 14 address/data timing: 60 mhz and 66 mhz (82438FX) ...................................... 14 timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 5 1.0 electrical characteristics 1.1 absolute maximum ratings warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. 1.2 thermal characteristics the 82437fx tsc and 82438FX tdp are designed for operation at case temperatures between 0 c and 85 c. the thermal resistances of the tsc and tdp packages are given in table 1 and table 2, respectively. table 1. absolute maximum ratings parameter maximum rating case temperature under bias 0 c to +85 c storage temperature -55 c to +150 c voltage on any pin with respect to ground -0.3 to vdd + 0.3 v supply voltage with respect to vss -0.3 to +6.5 v maximum power dissipation 2.0 w table 1. 82437fx (tsc) package thermal resistance parameter air flow meters/second (linear feet per minute) 0 (0) 1.0 (196.9) q ja (c/w) 31 24.5 q jc (c/w) 8.6 table 2. 82438FX (tdp) package thermal resistance parameter air flow meters/second (linear feet per minute) 0 (0) 1.0 (196.9) q ja (c/w) 89 67 q jc (c/w) 29 intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 6 datasheet addendum 1.3 dc characteristics table 3. 82437fx dc characteristics functional operating range (vdd = 5 v 5%, vdd3 = 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter min max unit notes v il1 input low voltage -0.3 0.8 v notes 1,6; vdd3=3.135v v ih1 input high voltage 2.2 vdd3 + 0.3 v notes 1,7; vdd3=3.6v v il2 input low voltage -0.3 0.8 v note 2; vdd=4.75v v ih2 input high voltage 2.2 vdd + 0.3 v note 2; vdd=5.25v v ol1 output low voltage 0.4 v note 3 v oh1 output high voltage 2.4 v note 3 i ol1 output low current 1 ma i oh1 output high current -1 ma i ol2 output low current 3 ma note 4 i oh2 output high current -2 ma note 4 i ol3 output low current 6 ma note 5 i oh3 output high current -2 ma note 5 i ih1 input leakage current 10 a 0v timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 9 table 6. cpu interface timing; 60 mhz and 66 mhz (82437fx) functional operating range (vdd = 5 v 5%, vdd3 = 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes min max min max t7 ads# setup time to hclkin rising 5.0 5.5 4 t7a w/r# setup time to hclkin rising 6.0 6.5 4 t8 be[7:0]# setup time to hclkin rising 5.0 5.5 4 t10 hitm# setup time to hclkin rising 6.0 6.5 4 t11 cache# setup time to hclkin rising 5.0 5.5 4 t11a m/io# setup time to hclkin rising 6.0 6.5 4 t12 d/c# setup time to hclkin rising 5.0 5.5 4 t13 hlock#, smiact# setup time to hclkin rising 5.0 5.5 4 t14 ads#, hitm#, w/r#, m/io#, d/c#, be[7:0], hlock#, cache#, smiact# hold time from hclkin rising 1.0 1.0 4 t15 a[31:3] setup time to hclkin rising 3.0 3.0 4 t16 a[31:3] hold time from hclkin rising 1.0 1.0 4 t17 a[31:3] output enable from hclkin rising 0.0 13.0 0.0 13.5 8 t18 a[31:3] valid delay from hclkin rising 2.0 13.0 2.0 13.5 3 0 pf t19 a[31:3] float delay from hclkin rising 0.0 13.0 0.0 13.5 5 t21 brdy# valid delay from hclkin rising 1.5 8.0 1.5 8.5 3 0 pf t22 na# valid delay from hclkin rising 1.5 8.0 1.5 8.5 3 0 pf t23 ahold valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t24 boff# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t25 eads# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t26 ken#/inv valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 10 datasheet addendum table 7. second level cache timing; 60 mhz and 66 mhz (82437fx) functional operating range (vdd = 5 v 5%, vdd3 = 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes minmaxminmax asynchronous and burst srams t27 coe# valid delay from hclkin rising 2.0 9.0 2.0 9.5 3 0 pf t28 tio [7:0] valid delay from hclkin rising 2.0 9.0 2.0 9.5 3 0 pf t28a tio[7:0] flow through delay to brdy#, na#, cwe[7:0]# 2.0 10.0 2.0 10.5 6 t29 tio[7:0] setup time to hclkin rising 2.0 2.5 4 t30 tio[7:0] hold time from hclkin rising 2.0 2.0 4 t31 twe# valid delay from hclkin rising 2.0 9.0 2.0 9.5 3 0 pf asynchronous srams only t32 cwe[7:0]# valid delay from hclkin rising 3.0 13.0 3.0 13.5 3 0 pf t33 caa[4:3], cab[4:3]# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf burst srams only t34 cwe[7:0]# valid delay from hclkin rising 2.0 9.5 2.0 10.0 3 0 pf t35 ccs# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t36 cads# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t37 cadv# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 11 table 8. dram interface timing; 60 mhz and 66 mhz (82437fx) functional operating range (vdd = 5 v 5%, vdd3 = 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes min max min max t42 ras[4:0]# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t42a moe# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 t44 cas[7:0]# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t46 ma[11:2] valid delay from hclkin rising on first clock after ras# assertion 2.0 9.0 2.0 9.5 3 0 pf, 13 ohms t47a maa[1:0], mab[1:0] valid delay from hclkin rising 2.0 8.0 2.0 8.5 3 0 pf t47b ma[11:2], max[1:0] flow through delay for a read cycle 2.0 12.5 2.0 13.0 6 leadoff, 0 pf t47c ma[11:2], max[1:0] valid delay from hclkin rising for a refresh cycle 2.0 12.5 2.0 13.0 3 leadoff, 0 pf t47d ma[11:2], max[1:0] valid delay from hclkin rising for pci-to-dram read cycle 2.0 16.0 2.0 16.5 3 leadoff, 0 pf t47e ma[11:2], max[1:0] valid delay from hclkin rising for a write cycle 2.0 18.0 2.0 18.5 3 leadoff, 0 pf table 9. pci clock timing; 60 mhz and 66 mhz (82437fx) functional operating range (vdd = 5 v 5%, vdd3 = 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes min max min max t49 pclkin high time 12.0 12.0 1 t50 pclkin low time 12.0 12.0 1 t51 pclkin rise time 3.0 3.0 1 t52 pclkin fall time 3.0 3.0 1 intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 12 datasheet addendum table 10. pci interface timing; 60 mhz and 66 mhz (82437fx) functional operating range (vdd = 5 v 5%, vdd3 = 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes min max min max t53 ad[31:0] valid delay from pclkin rising 2112113 min: 0 pf max: 50 pf t54 ad[31:0] setup time to pclkin rising 7 7 4 t55 ad[31:0] hold time from pclkin 0 0 4 t56 c/be[3:0]#, frame#, trdy#, irdy#, stop#, lock#, par, devsel# valid delay from pclkin rising 2112113 min: 0 pf max: 50 pf t57 c/be[3:0]#, frame#, trdy#, irdy#, stop#, lock#, par, devsel# output enable delay from pclkin rising 228 t58 c/be[3:0]#, frame#, trdy#, irdy#, stop#, lock#, par, devsel# float delay from pclkin rising 2282285 t59 c/be[3:0]#, frame#, trdy#, irdy#, stop#, lock#, par, devsel# setup time to pclkin rising 774 t60 c/be[3:0]#, frame#, trdy#, irdy#, stop#, lock#, par, devsel# hold time from pclkin rising 004 t61 phlda# valid delay from pclkin rising 29.029.03 min: 0 pf max: 50 pf t65 phld# setup time to pclkin rising 12 12 4 t66 phld# hold time from pclkin rising 0 0 4 t67 gnt[3:0] # valid delay from pclkin rising 29.029.03 min: 0 pf max: 50 pf t68 req[3:0]# setup time to pclkin rising 12 12 4 t69 req[3:0]# hold time from pclkin rising 004 t70 rst# low pulse width 1 ms 1 ms 7 timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 13 1.5 82438FX ac characteristics table 11. tdp interface timing; 60 mhz and 66 mhz (82437fx) functional operating range (vdd = 5 v 5%, vdd3 = 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes min max min max t71 hoe# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t72 moe# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t73 poe# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t74 mstb# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t75 madv# valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t76 pcmd [1:0] valid delay from hclkin rising 1.5 7.0 1.5 7.5 3 0 pf t77 plink[15:0] valid delay from hclkin rising 2.0 7.5 2.0 8.0 3 0 pf t78 plink[15:0] setup time to pclkin rising 3.0 3.5 4 t79 plink[15:0] hold time from pclkin rising 2.5 2.5 4 table 12. host clock timing; 60 mhz and 66 mhz (82438FX) functional operating range (vdd = 5 v 5%, vdd3 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes min max min max t80 hclk period 15.2 20.0 16.7 20.0 1 t81 hclk high time 5.5 5.5 1 t82 hclk low time 5.5 5.5 1 t83 hclk rise time 1.5 1.5 1 t84 hclk fall time 1.5 1.5 1 t85 hclk period stability 250 250 ps intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 14 datasheet addendum table 13. command signal timing; 60 mhz and 66 mhz (82438FX) functional operating range (vdd = 5 v 5%, vdd3 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes min max min max t86 moe# setup time to hclkin rising 3.0 3.5 4 t87 moe# hold time to hclkin rising 1.5 1.5 4 t88 hoe# setup time to hclkin rising 3.0 3.5 4 t89 hoe# hold time to hclkin rising 1.5 1.5 4 t90 poe# setup time to pclkin rising 3.0 3.5 4 t91 poe# hold time to pclkin rising 1.5 1.5 4 t92 madv# setup time to hclkin rising 5.0 5.5 4 t93 madv# hold time from hclkin rising 1.5 1.5 4 t94 mstb# setup time to hclkin rising 3.0 3.5 4 t95 mstb# hold time to hclkin rising 1.5 1.5 4 t96 pcmd[1:0] setup time to hclkin rising 4.0 4.5 4 t97 pcmd[1:0] hold time to hclkin rising 1.5 1.5 4 t98 plink[7:0] setup time to hclkin rising 3.0 3.5 4 t99 plink[7:0] hold time to hclkin rising 2.0 2.0 4 t100 plink [7:0] output valid delay to hclkin rising 2.0 9.0 2.0 9.5 3 0 pf table 14. address/data timing: 60 mhz and 66 mhz (82438FX) functional operating range (vdd = 5 v 5%, vdd3 = 3.135 v to 3.6 v; t case = 0 c to +85 c) symbol parameter 66 mhz 60 mhz fig. notes min max min max t101 d[31:0] valid delay from hclkin rising 1.4 7.5 1.4 8.0 3 0 pf t102 d[31:0] setup time to hclkin rising host bus 3.0 3.5 4 t103 d[31:0] hold time from hclk rising host bus 1.5 1.5 4 t104 md[31:0] valid delay from hclkin rising 1.7 11.0 1.7 11.5 3 0 pf t105 md[31:0] setup time to madv# falling 3.0 3.5 4 t106 md[31:0] hold time from madv# falling 1.0 1.0 4 timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 15 1.6 82437fx/82438FX timing diagrams figure 1. clock timing figure 2. propagation delay figure 3. valid delay from rising clock edge figure 4. setup and hold times figure 5. float delay hclkin pclkin clk_tm.vsd 2.0v 0.8v period high time low time fall time rise time output input a5059-01 propagation delay vt vt note: valid delay is from rising or falling clock edge to vt output clock a5060-01 valid delay vt 1.5v input clock a5061-01 setuptime hold time vt 1.5v vt input vt float delay output intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 16 datasheet addendum figure 6. flow through delay figure 7. pulse width figure 8. output enable delay flowthru.drw hclkin ads# a[31:3], be[7:0] ma[11:2], maa[1:0], mab[1:0] t47b,t47c note: the flow through delay is for the leadoff cycle during a dram access. t47b a5054-01 pulse width vt vt clock 1.5v output output enable delay timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 17 2.0 timing relationship diagrams 2.1 cache timing relationships figure 9. burst read (l1 line fill), standard sram abr.drw hclk ads# a[31:3] cache# d[63:0] brdy# ken# ca[4:3] coe# cwe[7:0]# tio[7:0] twe# intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 18 datasheet addendum figure 10. burst write (l1 cache write-back), standard sram figure 11. back to back burst reads (l1 cache line fills), standard sram abw.drw hclk ads# a[31:3] cache# d[63:0] brdy# ken# ca[4:3] coe# cwe[7:0]# tio[7:0] twe# hclk ads# a[31:3] cache# d[63:0] brdy# ken# ca[4:3] coe# cwe[7:0]# tio[7:0] twe# timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 19 figure 12. second level cache read miss, write-back, line fill with pipelined burst sram figure 13. read miss, l2 cache write-back, line fill, standard sram hclk ads# a[31:3] cache# d[63:0] brdy# ken# ca[4:3] coe# cwe[7:0]# tio[7:0] twe# abbw.drw armwblf.drw if ahold is asserted cpu address will tri-state if ahold is asserted tio[7:0] will transition hclk ads# a[31:3] cache# d[63:0] brdy# ken# ahold ca[4:3] coe# cwe[7:0]# tio[7:0] twe# intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 20 datasheet addendum figure 14. burst read, pipelined burst sram figure 15. back-to-back reads (l1 cache line fills), pipelined burst sram bbr.dr w hclk ads# brdy# na# a[31:3] d[63:0] w/r# cache# cadv# coe# ken# cads# ccs# bbbrp.drw hclk ads# brdy# na# a[31:3] d[63:0] w/r# cache# cadv# coe# ken# ccs# cads# timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 21 figure 16. back-to-back writes (l1 cache line fills), pipelined burst sram bbbwp.dr w hclk ads# brdy# na# a[31:3] d[63:0] w/r# cache# cadv# ken# cwe[7:0]# coe# ccs# cads# intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 22 datasheet addendum figure 17. l2 cache read miss, write-back, line fill, pipelined burst sram brmwblf.drw if ahold is asserted cpu address will tri-state if ahold is asserted tio[7:0} will transition hclk ads# a[31:3] cache# d[63:0] brdy# na# ken# ahold cads# ccs# coe# cadv# cwe[7:0]# twe# tio[7:0] timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 23 2.2 dram timing relationships figure 18. burst read page hit (edo) 000 001 010 011 nop ld nop td12.drw d0 d1 d2 d3 ld nop ld nop ld nop hclk ads# na# a[31:3]\be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# pcmd[1:0] plink[15:0] intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 24 datasheet addendum figure 19. burst read row miss (edo) 000 001 010 011 nop ld nop td16.drw d3 d2 d1 d0 ld nop ld nop ld nop hclk ads# na# a[31:3]\be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# pcmd[1:0] plink[15:0] timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 25 figure 20. burst read page miss (edo) 000 001 010 011 nop ld nop td17.drw d3 d2 d1 d0 ld nopld nopld nop hclk ads# na# a[31:3]\be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# pcmd[1:0] plink[15:0] intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 26 datasheet addendum figure 21. burst read page hit (standard page mode) 000 001 010 011 nop ld nop td01.drw d0 d1 d2 d3 ld nop ld nop ld nop d0 d1 d2 d3 hclkin ads# na# a[31:3]\be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# pcmd[1:0] plink[15:0] timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 27 figure 22. burst read row miss (standard page mode) nop nop ld td08.drw d0 d1 d2 d3 ld nop ld nop ld nop hclkin ads# na# a:31:3]/be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# pcmd[1:0] plink[15:0] intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 28 datasheet addendum figure 23. burst read page miss (standard page mode) nop nop ld td10.drw d0 d1 d2 d3 ld nop ld nop ld nop hclkin ads# na# a:31:3]/be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# pcmd[1:0] plink[15:0] timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 29 figure 24. posted burst write page hit qw0 1 2 3 qw0 1 2 3 td02.drw hclkin ads# na# a[31:3]/be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 30 datasheet addendum figure 25. burst write row miss 12 3 td09.drw d0 d1 d2 d3 qw0 hclkin ads# na# a[31:3]/be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 31 figure 26. burst write page miss 123 td11.drw d0 d1 d2 d3 qw0 hclkin ads# na# a[31:3]/be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 32 datasheet addendum figure 27. burst write qw0 1 2 3 qw0 1 2 3 td18.drw hclk ads# na# a[31:3]/be#[7:0] brdy# hd[63:0] ma[10:2] ras# cas# md[63:0] madv# mstb# hoe# moe# poe# timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 33 2.3 additional timing relationships figure 28. cpu to pci write cycle figure 29. cpu to pci memory read cycle 12 3456 78910111213141516 address d0 d3l 30h d0 nop ld shft d1 d2 d3 ldsw ld ldsw shft shft nop shft nop nop nop d0l d0h d1l d1h d2l d2h d1 d2 d3 c2pwr.dr w hclkin pclkin ads# na# brdy# hd[63:0] pcmd[1:0] plink frame# ad irdy# trdy# 12 3456 7 8910111213141516 address d0 d0l d0l d0h d0 nop ldlo nop same timing for either ads# case c2prd.drw hclkin pclkin ads# frame# ad[31:0] irdy# trdy# pcmd[1:0] plink hd[63:0] brdy# intel ? 82437fx (tsc) and 82438FX (tdp) timing specification 34 datasheet addendum figure 30. pci bus master to dram write cycle 1 2 3456 78910111213141516 nop adr0 d0 d1 ldlo ldhi nop d0l d0h d1ld1h d0 d2 adr0 17 18 19 20 21 22 23 24 25 26 28 27 29 30 32 31 d2 d3 ldlo ldhi d1 d3 d2h d3h d2l d3l leading edge based on setup to plink tri-state trailing edge based on hold for last pci mstb# cpu2pci write cpu2pci wr p2dwr1.drw hclkin pclkin ahold ads# ha eads# hitm# frame# ad devsel# irdy# trdy# pcmd[1:0] poe# plink mstb# madv# md timing specification intel ? 82437fx (tsc) and 82438FX (tdp) datasheet addendum 35 figure 31. pci bus master read from dram figure 32. ras only dram refresh cycle 12 3456 78910111213141516 nop adr0 d0 d1 ldloldhi d0l d0h d1l d1h d0 d2 adr0 17 18 19 20 21 22 23 24 25 26 28 27 29 30 32 31 d2 d3 ldloldhi d1 d3 d2h d3h d2l d3l cpu2dram write edo assumed cpu dat a ldlo ldlo ldhi nop ras# not delayed for snoop p2drd1.drw hclkin pclkin ahold ads# ha eads# hitm# frame# ad devsel# irdy# trdy# pcmd[1:0] poe# plink ras# cas# madv# md refresh.drw hclkin ras4# ras3# ras2# ras1# ras0# cas#[7:0] ma [10:0] |
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